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data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 figure: mechanical dimensions 1 1024mb ddr C unbuffered ddr1 udimm 184pin u dimm sdu01g64h3bj2sa - xxr 1gbyte in tsop technology rohs compliant environmental requirements: ? operating temperature (t a ) standard grade 0c to 70c ? operating humidity 10% to 90% relative humidity, nonconde nsing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c options: ? data rate / latency marking ddr 400 mt/s cl3 - 50 dd r 333 mt/s cl2.5 - 60 ? module density 1024mb with 16 dies and 2 ranks standard grade (t a ) 0c to 70c features: ? 184 - pin 64 - bit unbuffer ed dual - in - line double data rate s ynchronous dram module ? module organization: dual rank 128m x 64 ? v dd = 2 .5v 0. 2 v, v ddq 2 .5v 0. 2 v ? v dd = 2 . 6 v 0. 1 v, v ddq 2 . 6 v 0. 1 v (ddr400) ? 2.5v i/o ( sstl_2 compatible) ? serial presence detect with eeprom ? gold - contact pads ? this module is fully pin and functional compatible to the jedec pc - 3200 spec. and jedec - standard mo - 206 . (see www.jedec.org ) ? the pcb and all components are manufactured according to the rohs compliance specificat ion [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr - sdram component base: samsung k4h510838j die rev. j ? 64 mx8 ddr1 sdram in tsop66 package ? internal, pipelined double - data - rate (ddr) ? 2n pre - fetch architecture ? dll to align dq and dq s transitions with ck ? bidirectional data strobe (dqs) transmitted/received with data, source - synchronous data capture ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? four internal banks for concurrent operation ? data mask (d m) for masking write data ? programmable burst length: 2,4 or 8 ? adjustable data - output drive strength ? auto refresh (cbr) and self refresh, 8k refresh every 64ms ? 1 if no tolerances specified 0.15mm . 096 ( 2 . 45 ) pin 92 ( pin 184 on backside ) 5 . 250 ( 133 . 35 ) 1 . 2 5 0 ( 3 1 . 7 4 ) . 3 8 9 ( 9 . 9 0 ) . 6 9 3 ( 1 7 . 6 0 ) 2 . 893 ( 73 . 50 ) 4 . 744 ( 120 . 50 ) . 080 ( 2 . 03 ) r . 080 ( 2 . 03 ) r . 049 ( 1 . 25 ) r pin 1 ( pin 93 on backside )
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 this swissbit module family is industry standard 184 - pin 8 - byte double date rate synchronous sdram dual - i n - line memory modules (dimms), which are organized as x64 high speed memory arrays designed for use in non - parity applications. dimms are assembled in tsop technology. the passive devices and the eeprom are smd components. the dimm use serial presence dete cts (spd) implemented via serial eeprom using the two - pin - i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all swissbit dimms provide a high performance, flexible 8 - byte interfa ce in a 133.35mm long footprint. all modules of the extended temperature grade have seen special tests during the manufacturing process to ensure proper operation according to the field of operation as stated in the environmental conditions. module config uration organization ddr sdrams used row addr. device bank addr. col umn addr. refresh module bank select 128m x 64 bit 16 x 64m x 8 bit (512mbit) 13 ba0, ba1 11 8k s0#, s1# module dimensions in mm 133.35 (long) x 30(high) x 4.00 [max] (thickness) produ ct parameters part number module density transfer rate clock cycle/data bit rate latency sdu01g64h 3bj 2sa - 50r 1024mb 3.2 gb/s 5.0ns/400mt/s 3.0 - 3 - 3 sdu01g64h3bj 2sa - 60r 1024mb 2.7 gb/s 6.0ns/333mt/s 2.5 - 3 - 3 pin name a0 C a12 address inputs ba0, ba1 bank address inputs dq0 C dq63 data input/output dm0 C dm7 input data mask ras # row address strobe cas # column address strobe we # read / write enable cke0 C cke1 clock enable ck0 C ck1 clock inputs, positive line ck0 # C ck1# clock inputs, negative line dqs0 C dqs7 data strobes
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 s0 # C s1# chip select v dd power (2.5v 0.2v) v ddq dq power (2.5v 0.2v) v ddspd spd power v ref input/output reference v s s ground scl clock for presence detect sda serial data out for presence detect sa0 C sa2 slave addre ss select bus for presence detect nc no connection pin configuration front side back side pin # pin name pin # pin name pin # pin name pin # pin name 1 v ref 47 dqs8 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 dm8 3 v ss 49 nc 95 dq5 141 a10 4 dq1 50 v ss 96 v ddq 142 nc 5 dqs0 51 nc 97 dm0 143 v ddq 6 dq2 52 ba1 98 dq6 144 nc 7 v dd 53 dq32 99 dq7 145 v ss 8 dq3 54 v ddq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 v dd 11 v ss 57 dq34 103 nc 149 dm4 12 dq8 58 v ss 104 v ddq 150 d q38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ddq 61 dq40 107 dm1 153 dq44 16 nc 62 v ddq 108 v dd 154 /ras 17 nc 63 /we 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ddq 19 dq10 65 /cas 111 nc 157 /s0 20 dq11 66 v ss 112 v ddq 158 nc 21 cke0 67 dqs5 113 nc 159 dm5 22 v ddq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 v dd 116 v ss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 front side back side pin # pin name pin # pin name pin # pin name pin # pin n ame 26 v ss 72 dq48 118 a11 164 v ddq 27 a9 73 dq49 119 dm2 165 dq52 28 dq18 74 v ss 120 v dd 166 dq53 29 a7 75 nc 121 dq22 167 nc 30 v ddq 76 nc 122 a8 168 v dd 31 dq19 77 v ddq 123 dq23 169 dm6 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 d q55 34 v ss 80 dq51 126 dq28 172 v ddq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 nc 128 v ddq 174 dq60 37 a4 83 dq56 129 dm3 175 dq61 38 v dd 84 dq57 130 a3 176 v ss 39 dq26 85 v dd 131 dq30 177 dm7 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 nc 180 v ddq 43 a1 89 v ss 135 nc 181 sa0 44 nc 90 nc 136 v ddq 182 sa1 45 nc 91 sda 137 ck0 183 sa2 46 v dd 92 scl 138 /ck0 184 v ddspd
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 functional block diagramm 1024 mbyte ddr sdram dimm 2ranks; non - ecc
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 dc electrical characte ristics and operating conditions (0c t a + 70c ; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q 2.3 2.7 v i/o reference voltage v ref 0.49 x v dd q 0.51x v dd q v i/o terminatio n voltage (system) v tt v ref C 0.04 v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C 0.15 v input leakage current any input 0v v in v dd, v ref pin 0v v in 1.35v i i - 10 10 a output leakage current (dq s are disabled; 0v v out v ddq ) i oz - 10 10 a output levels: high current ( v out = v ddq - 0.373v,minimum v ref, minimum v tt ) low current ( v out =0.373v, maximum v ref, maximum v tt ) i oh i ol - 16.8 16.8 - - ma ma ac input operating conditions (0c t a + 70c ; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.310 - v input low (logic 0) voltage v il (ac) - v ref - 0.310 v i/o reference voltage v ref(ac) 0.49 x v dd q 0.51x v dd q v capacitance parameter symbol min max units input/output capacitance: dq , dqs c 10 4.0 5.0 pf input capacitance: command and address c 11 18 .0 27.0 pf input capacitance: /s 0,1 c 11 18.0 27.0 pf input capacitance: ck, /ck c 12 10.0 14.0 pf input capacitance: cke c 13 18.0 27.0 pf
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 i dd specifications and conditions (0c t a + 70c ; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) see note 1 on page 9 parameter & test condition max. symb ol 3200 - 3 . 0 - 3 - 3 2700 - 2 . 5 - 3 - 3 unit operating current *) : one device bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1000 880 ma operating current : *) one device bank; active - read - precharge; burst = 2; t rc = t rc (min); t ck = t ck (min);i out = 0ma; address and contr ol inputs changing once per clock cycle i dd1 1440 1120 ma precharge power - down standby current: all device banks idle; power - down mode; t ck = t ck (min); cke = (low) i dd2p 80 80 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min) ; cke= high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f 480 480 ma active power - down standby current: one device bank active; power - down mode; t ck = t ck (min);cke = low i dd3p 720 480 ma active standby current: cs# = high; cke = high; one device bank; active - precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 960 720 ma operating current: burst = 2; reads; continous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 3000 1160 ma operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 1440 1240 ma auto refresh current t rc = t rc (min) i dd5 3520 3280 ma t rc = 7.8125 s i dd6 80 80 ma self refresh current: ck e 0.2v i dd7 48 48 ma operating current *) : four device bank interleaving reads (bl =4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd8 3080 2920 ma *) value calcu lated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode.
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 ddr sdram component electrical characteristics and recommended ac operating conditions (0c t a + 70c ; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) see note 1 on page 9 ac characteristics 3200 - 3 . 0 - 3 - 3 2700 - 2 . 5 - 3 - 3 parameter symbol min max min max unit access window of dq s ck/ck# t ac - 0.50 +0.50 - 0.70 +0.70 ns ck high - level width t ch 0.45 0.55 0.45 0.55 t ck ck low - level width t cl 0.45 0.55 0.45 0. 55 t ck clock cycle time cl=2.0 t ck (2.0) 7.5 13.0 7.5 13.0 cl=2.5 t ck (2.5) 6.0 13.0 6.0 13.0 ns cl= 3.0 t ck (3.0) 5.0 13.0 - - ns dq and dm input hold time relative to dqs t dh 0.40 - 0.45 - ns dq and dm input setup time relative to dqs t ds 0.40 - 0.45 - ns dq and dm input pulse width ( for each input ) t dipw 1.75 - 1.75 - ns access window of dqs from ck/ck# t dqsck - 0.6 +0.6 - 0.6 +0.6 ns dqs input high pulse width t dqsh 0.35 - 0.35 - t ck dqs input low pulse width t dqsl 0.35 - 0.35 - t ck dqs C t dqsq - 0.40 - 0.45 ns write command to first dqs latching transition t dqss 0.72 1.28 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0.2 - 0.2 - t ck half clock period t hp t ch, t cl - t ch, t cl - ns data - out high - impedance window from ck/ck# t hz +0.7 +0.7 ns data - out low - impedance window from ck/ck# t lz - 0.7 - - 0.7 - ns address and control input hold time ( fast slew rate ) t ihf 0.6 - 0.75 - ns address and control input setup time ( fast slew rate ) t isf 0.6 - 0.75 - ns address and control input hold time ( slow slew rate ) t ihs 0.7 - 0.8 - ns address and control input setup time ( slow slew rate ) t iss 0.6 - 0. 8 - ns load mode register command cycle time t mrd 10 - 12 - ns adress and control input pulse width (for each input) t ipw 2.2 - 2.2 - ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs t hp - t qhs ns data hold skew factor t qhs - 0.5 - 0.6 ns
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 ac characteristics 3200 - 3 . 0 - 3 - 3 2700 - 2 . 5 - 3 - 3 parameter symbol min max min max unit active to precharge command t ras 40 70.000 42 70.000 ns active to read with auto precharge command t rap 15 - 15 - ns active to active/ auto refresh command period t rc 55 - 60 - ns auto refresh command period t rfc 70 - 72 - ns active to read or write delay t rcd 15 - 15 - ns precharge command period t rp 15 - 15 - ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 10 - 12 - ns dqs write preamble t wpre 0.25 - 0.25 - t ck dqs write preamble setup time t wpres 0 - 0 - ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck write recovery time t wr 15 - 15 - n s internal write to read command delay t wtr 2 - 1 - t ck data valid output window n /a t qh - t dqsq t qh - t dqsq ns refresh to refresh command interval t refc - 70.3 - 70.3 s average periodic refresh interval 0 c case t refi - 7.8 - 7.8 s 85 c < t case t refi (it) 3.9 3.9 terminating voltage delay to v dd t vtd 0 - 0 - ns exit self refresh to non - read command t xsnr 70 - 75 - ns exit self refresh to read command t xsrd 200 - 200 - t ck note 1: values for ac timing, i dd , and electri cal ac and dc characteristics might have been collected within the standard temperature range and at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified and for th e corresponding field of operation according to the actual temperature grade of the module (extended e, i or w; refer to the environmental conditions for more details).
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 serial presence - detect matrix byte description 3200 - 3 . 0 - 3 - 3 2700 - 2 . 5 - 3 - 3 0 number o f spd bytes used 0x80 1 total number of bytes in spd device 0x08 2 fundamental memory type 0x07 3 number of row addresses on assembly 0x0d 4 number of column addresses on assembly 0x0b 5 number of physical banks on dimm 0x02 6 module data width 0x40 7 module data width (continued) 0x00 8 module voltage interface levels (v ddq ) 0x04 9 sdram cycle time, (t ck ) (cas latency =2.5 (2700, 2100) ; cl=3* (3200) 0x50 0x60 10 sdram access from clock, (t ac ) (cas latency =2.5 (2700, 2100); cl=3* (3200)) 0x65 0x70 11 module configuration type 0x00 12 refresh rate/ type 0x82 13 sdram device width (primary sdram) 0x08 14 error - checking sdram data width 0x00 15 minimum clock delay, back - to - back random column access 0x01 16 burst lengths supported 0x0e 1 7 number of banks on sdram device 0x04 18 cas latencies supported 0x18 0x0c 19 cs latency 0x01 20 we latency 0x02 21 sdram module attributes 0x20 22 sdram device attributes: general 0xc0 23 sdram cycle time, (t ck ) (cas latency=2(2700, 2100) cl=2,5*( 3200)) 0x60 0x75 24 sdram access from ck, (t ac ) (cas latency=2(2700, 2100) cl=2.5*(3200) 0x70 25 sdram cycle time, (t ck ) (cas latency=1.5(2700, 2100) cl=2*(3200)) 0x00 26 sdram access from ck, (t ac ) (cas latency=1.5(2700, 2100) cl=2*(3200) 0x00 27 minimum row precharge time, (t rp ) 0x3c 0x48 28 minimum row active to row active, (t rrd ) 0x28 0x30 29 minimum ras# to cas# delay, (t rcd ) 0x3c 0x48 30 minimum ras# pulse width, (t ras ) 0x28 0x2a 31 module bank density 0x80 32 address and command setup ti me, (t is ) 0x60 0x80 33 address and coomand hold time, (t ih ) 0x60 0x80 34 data/data mask input setup time, (t ds ) 0x40 0x45 35 data/data mask input hold time, (t dh ) 0x40 0x45 36 - 40 reserved 0x00 41 min active auto refresh time (t rc ) 0x37 0x3c 42 minimu m auto refresh to active/ auto refresh command period, (t rfc) 0x46 0x48 43 sdram device max cycle time (t ckmax ) 0x28 0x30 44 sdram device max dqs - dq skew time (t dqsq ) 0x28 0x2d 45 sdram device max read data hold skew factor (t qhs ) 0x50 0x55
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 serial p resence - detect matrix (continued) byte description 3200 - 3 . 0 - 3 - 3 2700 - 2 . 5 - 3 - 3 46 - 61 reserved 0x00 62 spd revision 0x11 63 checksum for bytes 0 - 62 0xc0 0x69 64 manufacturer`s jedec id code 7f 65 manufacturer`s jedec id code 7f 66 manufacturer`s jedec id code 7f 67 manufacturer`s jedec id code (continued) da 72 manufacturing location 0x01 switzerland 0x02 germany 0x03 usa 73 - 90 module part number (ascii) sdu01g64h3bj2sa - xx 91 pcb identification code x 92 identification code (continued) x 9 3 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x x part number code s d u 01g 64 h 3 b j 2 sa - 50 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 * rohs compl. swissbit ag ddr - 400mhz sdram d dr 184 pin unbuffered 2.5v chip vendor (samsung) module c apacity (1 g b yte ) 2 module ranks module data w idth chip rev. j pcb - type ( bdsa83a ) chip organisation x8 * optional / additional information
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 revision history revision changes date 1 . 0 initial revision 1 8 .09 .2012
data sheet re v.1.0 18.09.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit. com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 13 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 ___________________________ __ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1202 e. winding creek drive eagle, id 83616 usa phone: +1 208 870 4525 fax: +1 208 870 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 _____________________________ ___

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